A large scale integration (LSI) chip is bonded on a surface of a package substrate or a circuit board by, for example, so-called the flip chip technology. The flip chip technology may be referred to as Controlled Collapse Chip Connection (C4) when solder bumps are used. Typically, the flip chip technology refers to a method for interconnecting semiconductor devices, such as IC chips, to external circuitry (e.g., the package substrate) with conductive bumps that have been deposited onto the chip pads. In performing the flip-chip bonding, an underfill material that includes resin is typically applied onto the surface of the package substrate. Then, the conductive bumps deposited on the LSI chip are aligned on corresponding contact pads provided on the surface of the package substrate. A plurality of LSI chips may also be simultaneously provided on a bulk circuit board (see, for example, Japanese Laid-Open Patent Applications 2002-324821, 2002-110744 and 2004-119594). Then, the underfill material is heated and cured. The mounting process of the LSI chip is completed by curing the underfill material. Thereafter, in the case where a plurality of LSI chips are provided on the bulk circuit board, the bulk circuit board is cut into separate package substrates according to the desired size of the LSI chip packages.
JP-A-2002-324821, for example, discloses the lower ends of bonding heads being pressed against an upper surface of respective LSI chips. During the manufacturing process, the respective bonding heads, such as T-shaped heads, are held or housed in a platform structure, and vertically moved with the platform with respect to the corresponding LSI chips. An elastic member is provided in the platform to balance out slight differences of vertical movements between the respective bonding heads. When the lower end of the bonding head contacts an upper surface of the LSI chip in response to a descending movement of the platform, certain pressing force is applied to the LSI chips by the respective bonding heads. The number and/or the size of such bonding heads may be determined depending on the size of the LSI chips and/or an interval between the LSI chips.